[Bug 2146724] [NEW] Request for CXL Support – Push Writes (Ultra-Low Latency) in Ubuntu 26.04

Private bug reported:

CXL Push Writes (Ultra-Low Latency) is an advanced capability in the
Compute Express Link (CXL) ecosystem that enables devices (e.g.,
accelerators, SmartNICs, memory expanders) to directly push data into
host memory or cache-coherent domains with minimal latency.

Unlike traditional pull-based or host-mediated data movement, push
writes allow devices to initiate memory updates without requiring CPU
intervention or explicit read cycles. This significantly reduces latency
and improves efficiency for data-intensive and latency-sensitive
workloads.

This feature is particularly important in next-generation platforms
leveraging CXL 3.x fabrics, where large-scale disaggregated memory and
accelerator sharing require fast, coherent, and low-overhead data
exchange. Push writes enable near load/store-like semantics across the
fabric, improving responsiveness for real-time processing, AI/ML
pipelines, and high-performance networking.

In the Linux kernel, support for CXL Push Writes requires enhancements
across memory management, cache coherency handling, IOMMU, and device
driver models. While the underlying capability is hardware-driven, the
OS must correctly manage synchronization, ordering, and visibility of
device-initiated writes.

Feature Request:
Requested details to be enabled on OS:
  Enable detection and enumeration of CXL push write capabilities. 
  Support device-initiated memory writes into host memory/coherent domains. 
  Ensure proper cache coherency and memory ordering for push-based updates. 
  Integrate with CXL.mem and CXL.cache subsystems in the OS. 
  Enhance IOMMU support for secure and efficient device-initiated writes. 
  Provide mechanisms for synchronization and visibility (e.g., barriers, notifications). 
  Support driver frameworks for push-based data movement models. 
  Expose configuration and status via sysfs/debugfs. 
  Enable performance monitoring and telemetry for push write operations. 
  Ensure compatibility with PCIe Gen6 and CXL 3.x fabrics. 
  Support virtualization environments (KVM/QEMU, SR-IOV, VFIO). 
  Provide validation and debugging tools for low-latency data paths. 
  Document usage models, constraints, and best practices.

Business Justification:
 Enables ultra-low-latency data movement across CXL fabrics.
 Reduces CPU overhead by eliminating unnecessary data polling and copies.
 Improves performance for AI/ML, HPC, and real-time analytics workloads.
 Enhances efficiency in disaggregated and composable infrastructure.
 Supports next-generation accelerator and memory architectures.
 Aligns with evolving CXL 3.x ecosystem and future data center designs.

References:
  CXL 2.0 / 3.0 / 3.1 Specifications 
  Linux Kernel CXL Subsystem Documentation 
  PCIe Gen6 and Coherent Interconnect Documentation 
  Industry Whitepapers on Disaggregated Memory and Accelerator Fabrics

** Affects: linux (Ubuntu)
Importance: Undecided
Status: New

** Information type changed from Public to Private

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https://bugs.launchpad.net/bugs/2146724

Title:
Request for CXL Support – Push Writes (Ultra-Low Latency) in Ubuntu
26.04

Status in linux package in Ubuntu:
New

Bug description:
CXL Push Writes (Ultra-Low Latency) is an advanced capability in the
Compute Express Link (CXL) ecosystem that enables devices (e.g.,
accelerators, SmartNICs, memory expanders) to directly push data into
host memory or cache-coherent domains with minimal latency.

Unlike traditional pull-based or host-mediated data movement, push
writes allow devices to initiate memory updates without requiring CPU
intervention or explicit read cycles. This significantly reduces
latency and improves efficiency for data-intensive and latency-
sensitive workloads.

This feature is particularly important in next-generation platforms
leveraging CXL 3.x fabrics, where large-scale disaggregated memory and
accelerator sharing require fast, coherent, and low-overhead data
exchange. Push writes enable near load/store-like semantics across the
fabric, improving responsiveness for real-time processing, AI/ML
pipelines, and high-performance networking.

In the Linux kernel, support for CXL Push Writes requires enhancements
across memory management, cache coherency handling, IOMMU, and device
driver models. While the underlying capability is hardware-driven, the
OS must correctly manage synchronization, ordering, and visibility of
device-initiated writes.

Feature Request:
Requested details to be enabled on OS:
  Enable detection and enumeration of CXL push write capabilities. 
  Support device-initiated memory writes into host memory/coherent domains. 
  Ensure proper cache coherency and memory ordering for push-based updates. 
  Integrate with CXL.mem and CXL.cache subsystems in the OS. 
  Enhance IOMMU support for secure and efficient device-initiated writes. 
  Provide mechanisms for synchronization and visibility (e.g., barriers, notifications). 
  Support driver frameworks for push-based data movement models. 
  Expose configuration and status via sysfs/debugfs. 
  Enable performance monitoring and telemetry for push write operations. 
  Ensure compatibility with PCIe Gen6 and CXL 3.x fabrics. 
  Support virtualization environments (KVM/QEMU, SR-IOV, VFIO). 
  Provide validation and debugging tools for low-latency data paths. 
  Document usage models, constraints, and best practices.

Business Justification:
 Enables ultra-low-latency data movement across CXL fabrics.
 Reduces CPU overhead by eliminating unnecessary data polling and copies.
 Improves performance for AI/ML, HPC, and real-time analytics workloads.
 Enhances efficiency in disaggregated and composable infrastructure.
 Supports next-generation accelerator and memory architectures.
 Aligns with evolving CXL 3.x ecosystem and future data center designs.

References:
  CXL 2.0 / 3.0 / 3.1 Specifications 
  Linux Kernel CXL Subsystem Documentation 
  PCIe Gen6 and Coherent Interconnect Documentation 
  Industry Whitepapers on Disaggregated Memory and Accelerator Fabrics

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