Private bug reported:
AMD Smart Data Cache Injection (SDCI) is a data acceleration feature
that optimizes data movement by allowing external agents (e.g.,
accelerators, DMA engines, I/O devices) to inject data directly into the
CPU cache hierarchy. Instead of writing data to main memory and relying
on the CPU to fetch it later, SDCI enables cache-level data placement,
reducing memory latency and bandwidth consumption while improving
performance for data-intensive workloads.
SDCI is particularly beneficial in scenarios involving high-throughput
data movement such as networking, storage, and accelerator pipelines,
where minimizing memory round-trips can significantly improve
efficiency. It complements other data mover technologies (e.g., SDXI) by
enhancing how data is consumed by the CPU after being transferred.
This feature requires tight coordination between hardware (CPU cache
hierarchy, interconnects), I/O subsystems, and software components to
ensure cache coherency, ordering, and correctness. It also introduces
considerations around cache management policies, security isolation, and
performance tuning.
In the Linux kernel, SDCI enablement involves support across DMA/IOMMU
subsystems, cache coherency management, and device drivers. While much
of the functionality is hardware-driven, the OS plays a role in
configuration, policy control, and exposing capabilities to applications
and drivers.
Feature Request:
Requested details to be enabled on OS:
Enable detection and enumeration of SDCI capabilities in the OS.
Provide kernel interfaces to control and configure cache injection behavior.
Integrate SDCI with DMA and IOMMU subsystems for coherent data placement.
Ensure cache coherency and correctness across CPU cores and devices.
Support driver-level enablement for SDCI-capable devices.
Expose SDCI configuration and status via sysfs/debugfs.
Enable performance tuning (cache policies, thresholds, prioritization).
Integrate with data mover frameworks (e.g., SDXI, DMA engines).
Support virtualization scenarios (KVM/QEMU, SR-IOV, VFIO).
Ensure isolation and security between tenants/workloads.
Provide monitoring and telemetry for cache injection efficiency.
Provide fallback mechanisms when SDCI is not available.
Document usage models, limitations, and best practices.
Business Justification:
Reduces memory latency and bandwidth usage.
Improves performance for data-intensive workloads (networking, storage, AI/ML).
Enhances efficiency of data pipelines and accelerator interactions.
Reduces CPU overhead by minimizing memory fetch operations.
Aligns with modern trends in data-centric computing and hardware acceleration.
Improves scalability in high-performance and cloud environments.
References:
AMD SDCI (Smart Data Cache Injection) Architecture Documentation
Linux Kernel DMA, IOMMU, and Cache Coherency Documentation
Industry Whitepapers on Cache Injection and Data Movement Optimization
** Affects: linux (Ubuntu)
Importance: Undecided
Status: New
** Information type changed from Public to Private
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https://bugs.launchpad.net/bugs/2146716
Title:
Request for Data Acceleration Support – AMD SDCI (Smart Data Cache
Injection) in Ubuntu 26.04
Status in linux package in Ubuntu:
New
Bug description:
AMD Smart Data Cache Injection (SDCI) is a data acceleration feature
that optimizes data movement by allowing external agents (e.g.,
accelerators, DMA engines, I/O devices) to inject data directly into
the CPU cache hierarchy. Instead of writing data to main memory and
relying on the CPU to fetch it later, SDCI enables cache-level data
placement, reducing memory latency and bandwidth consumption while
improving performance for data-intensive workloads.
SDCI is particularly beneficial in scenarios involving high-throughput
data movement such as networking, storage, and accelerator pipelines,
where minimizing memory round-trips can significantly improve
efficiency. It complements other data mover technologies (e.g., SDXI)
by enhancing how data is consumed by the CPU after being transferred.
This feature requires tight coordination between hardware (CPU cache
hierarchy, interconnects), I/O subsystems, and software components to
ensure cache coherency, ordering, and correctness. It also introduces
considerations around cache management policies, security isolation,
and performance tuning.
In the Linux kernel, SDCI enablement involves support across DMA/IOMMU
subsystems, cache coherency management, and device drivers. While much
of the functionality is hardware-driven, the OS plays a role in
configuration, policy control, and exposing capabilities to
applications and drivers.
Feature Request:
Requested details to be enabled on OS:
Enable detection and enumeration of SDCI capabilities in the OS.
Provide kernel interfaces to control and configure cache injection behavior.
Integrate SDCI with DMA and IOMMU subsystems for coherent data placement.
Ensure cache coherency and correctness across CPU cores and devices.
Support driver-level enablement for SDCI-capable devices.
Expose SDCI configuration and status via sysfs/debugfs.
Enable performance tuning (cache policies, thresholds, prioritization).
Integrate with data mover frameworks (e.g., SDXI, DMA engines).
Support virtualization scenarios (KVM/QEMU, SR-IOV, VFIO).
Ensure isolation and security between tenants/workloads.
Provide monitoring and telemetry for cache injection efficiency.
Provide fallback mechanisms when SDCI is not available.
Document usage models, limitations, and best practices.
Business Justification:
Reduces memory latency and bandwidth usage.
Improves performance for data-intensive workloads (networking, storage, AI/ML).
Enhances efficiency of data pipelines and accelerator interactions.
Reduces CPU overhead by minimizing memory fetch operations.
Aligns with modern trends in data-centric computing and hardware acceleration.
Improves scalability in high-performance and cloud environments.
References:
AMD SDCI (Smart Data Cache Injection) Architecture Documentation
Linux Kernel DMA, IOMMU, and Cache Coherency Documentation
Industry Whitepapers on Cache Injection and Data Movement Optimization
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