[Bug 2146639] [NEW] Request for CXL DRAM Command Interface Support

Private bug reported:

Compute Express Link (CXL) introduces a new paradigm for memory
expansion and pooling, where DRAM attached to external devices (CXL
Type-3 memory devices) is accessed over the PCIe physical layer using
CXL protocols. In this architecture, the traditional DRAM command
interface (ACT, PRE, RD, WR, REF, MRS, etc.) is abstracted behind the
CXL device controller, and the host interacts with memory using higher-
level load/store semantics via CXL.mem.

In the Linux kernel, CXL support (via the CXL subsystem and drivers such
as cxl_core, cxl_mem) enables discovery, configuration, and management
of CXL-attached memory. However, visibility into underlying DRAM command
behavior (e.g., command retries, media errors, timing constraints) is
limited. Enhancing support would improve observability and reliability
for next-generation memory architectures leveraging CXL.

Feature Request:
Requested details to be enabled on OS:

 Enhance CXL subsystem (cxl_core, cxl_mem) to expose DRAM command-related telemetry abstracted by CXL devices. 
 Integrate CXL memory error reporting with EDAC and RAS frameworks. 
 Support reporting of internal media events (e.g., command retries, refresh issues, parity/ECC events). 
 Provide sysfs/debugfs interfaces for monitoring CXL memory device health and command behavior. 
 Enable firmware-to-OS handoff of CXL memory characteristics and command-related constraints. 
 Support advanced CXL RAS features (poison handling, error containment, media scrub reporting). 
 Ensure compatibility with memory pooling and multi-headed CXL configurations. 
 Enable tracing/logging for performance bottlenecks related to internal DRAM command scheduling. 
 Document CXL memory device behavior, limitations, and observability mechanisms.

Business Justification:
- Improves observability of CXL-attached memory health and performance.
- Enhances reliability and RAS capabilities for memory expansion and pooling use cases.
- Enables efficient debugging of memory-related issues in disaggregated architectures.
- Supports adoption of CXL-based infrastructure in data centers and hyperscale environments.
- Aligns OS capabilities with emerging CXL memory ecosystem and standards.

References:
–  CXL 2.0 / 3.0 Specification (CXL.mem) 

 Linux Kernel CXL Subsystem Documentation 
 JEDEC DRAM Standards (DDR5, MRDIMM) 
 Linux EDAC Subsystem Documentation

** Affects: linux (Ubuntu)
Importance: Undecided
Status: New

** Information type changed from Public to Private

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https://bugs.launchpad.net/bugs/2146639

Title:
Request for CXL DRAM Command Interface Support

Status in linux package in Ubuntu:
New

Bug description:
Compute Express Link (CXL) introduces a new paradigm for memory
expansion and pooling, where DRAM attached to external devices (CXL
Type-3 memory devices) is accessed over the PCIe physical layer using
CXL protocols. In this architecture, the traditional DRAM command
interface (ACT, PRE, RD, WR, REF, MRS, etc.) is abstracted behind the
CXL device controller, and the host interacts with memory using
higher-level load/store semantics via CXL.mem.

In the Linux kernel, CXL support (via the CXL subsystem and drivers
such as cxl_core, cxl_mem) enables discovery, configuration, and
management of CXL-attached memory. However, visibility into underlying
DRAM command behavior (e.g., command retries, media errors, timing
constraints) is limited. Enhancing support would improve observability
and reliability for next-generation memory architectures leveraging
CXL.

Feature Request:
Requested details to be enabled on OS:

 Enhance CXL subsystem (cxl_core, cxl_mem) to expose DRAM command-related telemetry abstracted by CXL devices. 
 Integrate CXL memory error reporting with EDAC and RAS frameworks. 
 Support reporting of internal media events (e.g., command retries, refresh issues, parity/ECC events). 
 Provide sysfs/debugfs interfaces for monitoring CXL memory device health and command behavior. 
 Enable firmware-to-OS handoff of CXL memory characteristics and command-related constraints. 
 Support advanced CXL RAS features (poison handling, error containment, media scrub reporting). 
 Ensure compatibility with memory pooling and multi-headed CXL configurations. 
 Enable tracing/logging for performance bottlenecks related to internal DRAM command scheduling. 
 Document CXL memory device behavior, limitations, and observability mechanisms.

Business Justification:
- Improves observability of CXL-attached memory health and performance.
- Enhances reliability and RAS capabilities for memory expansion and pooling use cases.
- Enables efficient debugging of memory-related issues in disaggregated architectures.
- Supports adoption of CXL-based infrastructure in data centers and hyperscale environments.
- Aligns OS capabilities with emerging CXL memory ecosystem and standards.

References:
–  CXL 2.0 / 3.0 Specification (CXL.mem) 

 Linux Kernel CXL Subsystem Documentation 
 JEDEC DRAM Standards (DDR5, MRDIMM) 
 Linux EDAC Subsystem Documentation

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